(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to the formation of field isolation in memory arrays.
(2) Introduction and Description of Prior Art
Computer memory consist of vast arrays of storage cells which can be addressed by wordlines and bitlines. The most commonly used DRAM (dynamic random access memory) cell design comprises a transfer gate(usually an MOS field-effect-transistor(MOSFET) and a storage node consisting of a capacitor plate connected to the MOSFET drain. Memory cells for ROMs (read only memories), PROMS (programmable ROMs) and EEPROMs (electrically erasable PROMS) are similarly arranged in rectangular arrays and are addressed by wordlines and bitlines but typically have their storage nodes formed by a floating gate which lies subjacent to an addressable control gate. Memory cells require a high cell density in order to achieve high performance and cost efficiency.
The simplicity of cell design permits the interconnection of elements of the transfer MOSFET, thereby permitting simpler and more effective array design. Notably, the control gates of all the MOSFETs of a wordline may be formed of a single polysilicon band, traversing alternately over field oxide and cell gate regions. Likewise, the sources of the MOSFETs in a DRAM bitline string may be formed of a single diffusion or individual source diffusions, isolated by field oxide, may be interconnected by a superjacent addressable bitline. The interconnection of source elements by a diffusion band is found in EEPROM memory arrays. The drains of each of the MOSFETs must however remain unique and therefore electrically isolated.
The necessary field isolation for memory circuits is typically provided by a relatively thick layer of silicon oxide formed by the well known LOCOS (Local oxidation of silicon) process. For a conventional flash EPROM memory array, the field isolation regions are formed by a pattern of rectangular islands
In FIG. 1 there is shown a planar view of a region on a wafer upon which a LOCOS oxidation mask 20 for a memory cell array 10 has been patterned by a prior art process. The openings 25 expose rectangular areas of silicon 22 which are to be oxidized to form islands of field oxide (FOX). FIG. 2 shows the same region after the LOCOS oxidation has been performed and the oxidation mask has been stripped. The FOX islands provide the required isolation between the elements of the MOSFET devices which are to be formed in the active areas 28 and 30. The MOSFETs are formed by growing a gate oxide(not shown) over the active areas 28,30, patterning polysilicon gate electrode stripes 26 over the array 10 and finally forming source regions 30 and drain regions 28 by ion implantation. The source/drain elements are self-aligned to the gate electrode stripes 26. The source active areas 30 for each MOSFET are connected along the columns by a continuous source diffusion along the columns 31. The drains 28 are isolated in each cell by the FOX regions.
Forming the FOX isolation stripes in this manner leads to problems of birds beak encroachment into the active regions between the ends of the short stripes. Referring to FIG. 2, the birds beak encroachment, shown by the dotted line 32 is caused by the penetration of oxide under the LOCOS mask which reduces the effective width 34 of the source diffusion in this region. In order to compensate for this reduction, the spacing between the FOX line ends must be increased. This problem is discussed in some detail by Tang, et.al U.S. Pat. No. 5,103,274, and Tang, et.al. U.S. Pat. No. 5,120,671 in the formation of an EPROM, Flash EPROM, or EEPROM. The problem is overcome by these references by growing the FOX isolation as one long stripe and, after both floating polysilicon gates and the polysilicon control gate lines have been patterned, a mask is applied which protects the FOX isolating the drain regions and exposes the FOX between two adjacent polysilicon control gate lines. The exposed FOX is then etched out by reactive ion etching(RIE) forming short FOX stripes with vertical walled ends. The source regions which are subsequently formed, are self aligned to the polysilicon gate lines as also are the ends of the FOX islands. In order to self-align on the gate lines, an edge portion of the gate line is exposed to the FOX RIE.
Liu, U.S. Pat. No. 5,534,455 points out problems encountered by the method of Tang, '274, and Tang, '671 which include damage and undercutting of the gate or tunnel region beneath the gate stack as well as the formation of a silicon step resulting from over-etching of the FOX. The problem is overcome by Liu, by forming a sidewall along the poly gate line stack which protects the gate or tunnel region and displaces the over-etch step.
Ong, et.al., U.S. Pat. No. 5,466,624 cites a method for introducing an additional stripe of FOX isolation to establish a pair of adjacent drain diffusions. The memory arrays formed are of the floating gate type as found in EEPROMs. During processing, long FOX isolation stripes are formed which are subsequently segmented by a selective oxide etch. The segments provide isolation alongside the channel regions of the MOSFETs. Unlike Tang, '274, and Tang, '671, the floating gate polysilicon and the FOX sections are successively etched using the same mask. Thus the gate polysilicon is not partially exposed during the FOX etching but is covered by the mask and a nitride layer. Like Tang, '274, and Tang, '671, however, the ends of the FOX islands are aligned with an edge of the floating gate polysilicon.
Not all EEPROM designs permit this alignment commonality however. The floating gate pattern often does not coincide with the edge of the source diffusion outside of the channel region, in particular where the common source channel passes between FOX regions. This can be seen in the structure of a flash EEPROM cites by Liang, et.al., U.S. Pat. No. 5,714,412 where the floating gate edges are not aligned with the ends of the FOX islands. Clearly, it is not always possible to cut a FOX stripe into segments by the same etchant operation which patterns the floating gate in the manner of Ong, et.al.
Etching the FOX segments after the floating gate has been patterned in the manner of Tang, '274, and Tang, '671, requires the exposure of a portion of the floating gate to the FOX etchant. This would not be possible in cases where the polysilicon gate stack has an oxide cap layer over it as in the manufacture of a split gate flash EEPROM by the ETOX.TM. (EEPROM with Tunnel OXide) process cited by Liang, et.al., '412.
McElroy, U.S. Pat. No. 4,373,248 also addresses the formation of a floating gate memory array having diffusion interconnected strings of sources and drains which are connected to column decoders. Long stripes of FOX isolation are employed but they are not subsequently segmented into smaller units.